I have a question about visual analog program's fpga configuration.
Is configuration of mechanism overwrite on fpga?
Or is there have default pin for just setting once and when I turn off it goes to before?
The ADI Product specific FPGA configuration is initially loaded by our VisualAnalog software tool as shown in your screen capture above. The configuration will remain in the FPGA until power is cycled on the HSC-ADC-EVALCZ. Cycling the power to the HSC-ADC-EVALCZ clears the dynamic FPGA configuration.
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