Hi, we're using ad9371 evaluation board with zynq zc706. We're building an application (no-OS) using the hdl and sw from github 2016_r2 branch. We need RX/TX rate of 110MHz. This rate couldn't be generated using on board 122.88MHz vcxo, so we replaced the on board vcxo with a 40 MHz one (we had this one available at the time). Then, we generated a custom profile with 80Mhz ref clk (using matlab filter wizard) and enabled ad9528 pll2 input R1 doubler to generate profile assumed 80MHz ref clk from 40MHz vcxo clk (ad9528.c). Assuming tx rate of 110MHz, and default settings of 4 lanes for tx, tx lane rate becomes 2.2GHz which cannot be generated with gtx qpll, so we switched to cpll (jesd_core.c -> xcvr_setup -> tx_xcvr.cpll_enable=1;) . The receiver side certainly works fine but the tx side gets tx_deframer=0x21 error. I wonder what other configuration we have to make to achieve tx rate of 110 MHz.
Thank you in advance.