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Phase lock issue with fmcadc4

Question asked by michellelloyd on Jan 29, 2018
Latest reply on Mar 2, 2018 by AdrianC

I am using the fmcadc4 evaluation board with the ZC706.  I use a signal generator to provide a 250 MHz input to channel A, and I input the 10 MHz reference clock to REF IN on the fmcadc4.  I have updated the AD9528 settings to look for an external reference clock, and I check the status registers of the AD9528 to make sure that it sees the reference and that PLL1 and PLL2 are able to lock.  I capture the ADC data on ILA at the output of axi_ad9680_core_0 and post-process in Matlab to calculate the frequency and phase of the signal.

 

I would expect that at 1 GHz sampling frequency, the phase of my 250 MHz input signal would be constant across time because I am locked to the 10 MHz reference output by the signal generator.  However, this is not the case - the phase is different every time I capture the data.

 

Has anyone else run into this?  Does anyone have any suggestions for things I should check in my system to make sure everything is locked?

 

Thanks in advance for your help,

Michelle

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