We have a custom design with the AD9361 which interfaces to a Zynq chip. We have fully tested and characterized the functionality of the AD9361 through software using the 2016_r1 Linux release for our hardware without any problems. After making some slight adjustments (none directly to the AD9361 pins, power supplies, or clocks) for a re-spin, we are having this RX LO Calibration timeout, seemingly without any other issues. All of the software we have tried, including the iio oscilloscope, low level c code, writes/reads directly from the rootfs iio handles, and no OS builds return the same error code. TX works perfectly fine. Attached is the boot log of Linux, where the error is clearly visible. We have verified that the clock reaching the AD9361 is a stable 40 MHz, with a peak to peak of ~1.2 V and an average value of 637 mV (it is supposed to be AC coupled so is this okay?). I realize the difficulty of determining the problem for a custom piece of hardware without including design files, but which places should I look for more information? Am I right in pursuing the input clock (single ended into XTAL_N pin) as the problem? I also attached a screenshot of the input clock and some other debug info in my Linux build.