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FMCDAQ2 ADC sampling  250MHZ RX 2 Lanes

Question asked by cerasic on Jan 29, 2018
Latest reply on Jan 31, 2018 by cerasic

Hi all,

First of all, many thanks to the support team specially Istvan, Lars, Rejeesh and all they  helped me to come to

point where I get the configuration FMCDAQ2 R2017R1 hdl and No-OS working with an ADC sampling rate of 250 Mhz.

 The 250MHZ sampling is not possible with hdl R2017_R1 because the Lane rate would be too low  for the 4 lanes of the RX path. Solution is to reduce the number of Lanes 2 instead of 4  on the RX path to get ADC 250 MSPS working. I will summarize in the following  how I got it working thanks to the support team.

The sofware No-OS R2017_R1 can be easily modified but the hardware,  I had to start with  the branch dev_ad9694, of the project ad9694_500ebz.     https://github.com/analogdevicesinc/hdl/tree/dev_ad9694

in the following I list everything I have done to get this configuration ADC 250 MSPS DAC 1000MSPS 

2 lanes RX / 4 Lanes TX

      Kind regards

 

A) Hardware change

1) Download the  hdl  (link above)
2) modify the file projects/daq2/common/daq2_bd.tcl   to change from 4 lanes to 2 Lanes as

   #ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES 4
   ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES 2

   #adi_axi_jesd204_rx_create axi_ad9680_jesd 4
   adi_axi_jesd204_rx_create axi_ad9680_jesd 2

   #ad_ip_parameter axi_ad9680_cpack CONFIG.CHANNEL_DATA_WIDTH 64
   ad_ip_parameter axi_ad9680_cpack CONFIG.CHANNEL_DATA_WIDTH 32

   #ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
   #ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
   ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 32
   ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 32

   #ad_ip_parameter util_daq2_xcvr CONFIG.RX_NUM_OF_LANES 4
   ad_ip_parameter util_daq2_xcvr CONFIG.RX_NUM_OF_LANES 2

3) modify the subblock axi_ad9680.v

      rx_data  64 instead of 128 bit

       adc_data_0 32 instead of 64 bits

       adc_data_1 32 instead of 64 bits

      the parameter .NUM_LANES (2) instead .NUM_LANES (4)   of the instance axi_adc_jesd204

4) modify system_top.v:  change  the bus rx_data_p / rx_data_n       2 bits instead of 4

5) modifify system_const.xdc:  comment   rx_data_p /rx_data_n         bit 2 and 3

 

B Sofware change   (the no-OS R2017_R1)

1)   change adc9680.c

       // ad9680_spi_write(dev, AD9680_REG_JESD204B_QUICK_CONFIG, 0x88);    // m=2, l=4, f= 1

       ad9680_spi_write(dev, AD9680_REG_JESD204B_QUICK_CONFIG, 0x49);    // m=2, l=2, f= 2

2) change fmcdaq2.c  :

    //ad9680_jesd.octets_per_frame = 1;

    ad9680_jesd.octets_per_frame = 2;
 

The setting for ADC  250 MSPS; DAC 1000 MSPS

            printf ("2 - ADC  250 MSPS; DAC 1000 MSPS\n\r");
            p_ad9523_param->pll2_vco_diff_m1 = 3;
            (&p_ad9523_param->channels[DAC_FPGA_CLK])->channel_divider = 2;
            (&p_ad9523_param->channels[DAC_DEVICE_CLK])->channel_divider = 1;
            (&p_ad9523_param->channels[DAC_DEVICE_SYSREF])->channel_divider = 128;
            (&p_ad9523_param->channels[DAC_FPGA_SYSREF])->channel_divider = 128;
            (&p_ad9523_param->channels[ADC_FPGA_CLK])->channel_divider = 4;
            (&p_ad9523_param->channels[ADC_DEVICE_CLK])->channel_divider = 4;         
            (&p_ad9523_param->channels[ADC_DEVICE_SYSREF])->channel_divider = 256;
            (&p_ad9523_param->channels[ADC_FPGA_SYSREF])->channel_divider = 256;
            p_ad9144_xcvr->reconfig_bypass = 0;
            p_ad9144_param->lane_rate_kbps = 10000000;
            p_ad9144_xcvr->lane_rate_kbps = 10000000;
            p_ad9144_xcvr->ref_clock_khz = 500000;
            p_ad9680_xcvr->reconfig_bypass = 0;

            p_ad9144_xcvr->dev.lpm_enable = 0;
            p_ad9144_xcvr->dev.qpll_enable = 1;
            p_ad9144_xcvr->dev.out_clk_sel = 4;    
            p_ad9680_param->lane_rate_kbps = 2500000;
            p_ad9680_xcvr->lane_rate_kbps = 2500000;
            p_ad9680_xcvr->ref_clock_khz = 125000;                        
            p_ad9680_xcvr->dev.lpm_enable = 1;
            p_ad9680_xcvr->dev.qpll_enable = 0;
            p_ad9680_xcvr->dev.out_clk_sel = 4;  // 0,1,2   this parameter seems to be irrelevant in this case

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