I am using 480p script to run the 7612 on the eval and this is detected by the 7511 and a color space is created. If I try to use a 37Mhz clock and syncs from my CPLD the HDMI clocks do not turn on.
Yes, the ADV7511 can handle that format. I am not sure which reference board you are looking at. The ADV7511 is basically a parallel to serial converter tuned for handling video streams to HDMI. I'd start with a AVG script to configure the ADV7511, it should work for you format.
I have the ADV7612 to ADV7511 eval board. I have entered in the script for 480p and the 7511 creates a colorspace output on HDMI monitor. I have taken note of the sync signals going to the ADV7511. My target board is driving an LCD with 37 MHz pixel clock. I have a cpld on my board that is bringing in video data and creating h, v and de signals for the LCD. I have created H, V and de signals similar to the eval board but the h syncs are closer together due to the faster clock. I am restrained by the video color data timing used for the LCD. If I send clock, H, V and De to the eval board ADV7511 inputs from my cpld, the HDMI clocks do not turn on.
Are you re-running the script to init the ADV7511?
So the target board converts 800x480p60 HDMI to what's needed by the LCD. Sounds like the format the CPLD is producing is not right. When the CPLD creates the format does it include all the blanking intervals?
Thanks for the fast reply
When I connect my clock and sync lines to the 7511, i re-init the 7511 with the 480p script.
Due to the timing required by the LCD that I can't change, the V syncs are at 20ms. Th 7612 creates V syncs at 16.68 ms. The H sync signals are 31.7 us apart for the Eval board. My cpld has H syncs 25 us apart. De signals are active during the H syncs.. I can widen the V sync duration on the cpld but I can't change the period.
Somethings not adding up here. You want an 800x480p50 output but I think your timing is missing the blanking intervals. At minimum HS pulse should be Vsync time / 480 = 40us and this is not including the blanking interval.
If we look at 640x480p60, one line is 800 clocks long. So there is 160 clocks of blanking and sync timing. I don't think your CPLD is including the blanking intervals
You can fine the VESA standards here
to compare against what you are trying to do. Look for DMT pdf.
The ADV7612 16.68 MHz is probably because the 7612 is running free mode 480p60.
If I understand correctly, with my 37 MHz clock (27ns) and 25 us H syncs (800 clocks * 27ns =~ 20us
The 25 MHz clock at 40ns (800*40ns =~ 32us). My Question, is the 37 MHz and my restraints compatible with 800x480 HMDI?
If your LCD displays 800 pixel across and 480 lines vertical at 60 Hz
HS width = 6 pixels
HFront porch = 20 pixels
HBack porch = 14 pixels
then H total pixels = 800 + 6 + 20 + 14 = 840
VS width = 2 lines
VFront porch = 164 lines
VBack porch = 14 lines
then V total lines = 480 + 2 + 164 + 14 = 660
this gives us
horizontal freq = 60 * 660 = 39.6kHz
pixel clock = Hfeq * 840 = 33.264MHz
Now I looked up some 800x480 (WVGA) panels and their usage. The driver directly driving the LCD does use the 800x480 timing. However any HDMI signalling has at least 5% if not more blanking interval for overhead. The chip converting HDMI to LCD signals converts the 33.264MHz to whatever the LCD panel needs. The key is to feed the LCD input chip with the right timing format. Assuming you have a demo system for the LCD panel where it can display a default image from the HDMI input, the TMDS clock line will be the pixel rate. You can measure this with a scope. The TMDS clock line should be ~3Vdc with a 33.264MHz +-300mV square wave riding on it.
Is the 37MHz clock form the CPLD fixed?
Thanks GunterL, this is good information
At this point, the LCD signals(and clock) can’t be changed without a decision that is above my head! If I use a different clock for the HDMI, I will probably not have the speed I need since I have to use the data as it is available for the LCD.
I will look at the numbers again and contemplate a course of action.
Another thought I had was to use a higher resolution format and not populate all the pixels. Any ideas??
I fixed the numbers in my previous post, the numbers just didn't add up. No change to end result
A higher resolution will not help. You need to figure out exactly what input HDMI the LCD panel needs. I should be somewhere in the data sheet for the module. Once you know this you can match the CPLD output to it.
Hello GunterL One More Question
Since the ADV7511 is a special Parallel to serial converter of sorts, will it output HDMI clocks and signals if they are not fit to a specific standard? Does it filter out input setups that are not part of an internal data base?
The ADV7511 doesn't know anything about specific formats. It just outputs the input timing with some constraints that are HDMI related. None of these constraints should effect you.
Is there a document that explains these constraints?
The basic constraints are
1) Frequency limitations, you are no where near these
2) Required blanking areas. Infoframes and audio packets ride in the blanking areas. Again you don't have either so they don't affect you
OK Thanks GunterL
I am a bit confused. If I am not overstepping the constraints, should I be seeing the HDMI clocks and Data coming up in non-standard configuration? I am not seeing that, maybe my issues are more basic
Yes, if you are feeding it proper clock and syncs you should see activity on the TMDS clock line assuming the sink (LCD panel) is providing the right loads on the TMDS lines.
What voltage, measured with a DVM, do you see on the TMDS lines when you think you've initialized the 7511 correctly?
With scope do you see any square wave on tmds clock line? Should be your pixel clock
We are seeing TDMS activity and the remote display appears to respond to the 480p script when it is run. There is no display but at least a starting point. Thanks for the support
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