Using AD9910 for sawtooth generation
I assume you are referring to an amplitude sawtooth (as opposed to a frequency sawtooth). In which case, start with the DDS set for sine output (default) and clear the phase accumulator.
Next, use one of the profiles to set the DDS for 0Hz with a phase offset of 270 degrees. This ensures that when the DDS phase accumulator is at zero (i.e., cleared), the DDS output is at negative full scale amplitude.
Next, set up the digital ramp generator (DRG) so that its destination is amplitude (the DRG can control the amplitude, phase or frequency of the DDS, so you must specify which one). Then program the DRG to produce the desired up/down ramp pattern. You can set up the DRG to output one sawtooth pulse or have it ramp up/down continuously to generate a continuous sawtooth pattern.
The data sheet describes the DRG features in detail.
Kenny thank you. This is very helpful.
However, I did not see an answer to my last question: What will be the settling time from the top of the sawtooth back to the bottom beginning, which basically is negative one frequency step of 11MHz?
I am not 100% certain, but I believe that once the sawtooth hits the final value of the ramp up sequence the DRG will return to the start value in 1 or 2 cycles of SYNC_CLK.
To be sure: Data sheets says "SYNC_CLK is a rising edge active signal. It is derived from thesystem clock and a divide-by-4 frequency divider"
I am using 1GHz REF clock. That means that the SYNC_CLK is 250MHz? One cycle will be 4nS? So DRG will return to start value in 4 or 8nS?
Does it also depend on the SCLK?
You sais that you are not 100% sure. can you verify? I will really be thankful.
SCLK only clocks data to/from the SPI port. It has no other functionality.
Yes, with a 1GHz system clock the DRG should return to the start value 4-8ns after reaching the final value. However, I am unable to verify. Perhaps someone else on the forum can confirm the DRG timing.
Do you have an AD9910 Evaluation Board? If so, it would be fairly easy to check.
Thank you for your help.
I understand about the SYNC_CLK and the settling time.
But I want to go back to your first answer. I think there is a confusion here:
I want to perform a frequency sawtooth and not an amplitude sawtooth. In other words, change of about 20 MHz over a period of about 90µS with PRF of about 10 KHz. (With some short delay between end of one sawtooth to the next one.
Can you instruct me again of how to perform it in the AD9910?
With the AD9910, amplitude, phase or frequency sawtooth generation is essentially the same. The device's DRG generates a 32-bit discreet step linear ramp, which can be used to control the DDS's frequency, phase or amplitude parameter. The data sheet explains how to use and program the DRG to generate almost any kind of ramp.
Programming the sawtooth is fairly simple. You program the desired lower and upper values. If you have set the DRG to control frequency, then the lower and upper values constitute lower and upper frequency tuning words. To control the slope of the sawtooth, you program two parameters: a step size and a step rate (actually, there are two slopes, because you have control the rising and falling portions of the ramp independently).
The step size and rate are interrelated as you can take many small steps at a high rate or a few large steps at a low rate. The step rate period is 4*K*ts, where ts is the system clock period and K is the integer associated with the step rate register. With a 1GHz system clock, for example, ts=1ns yielding a 4ns minimum step period. As you can see, implementing a 90us ramp is not a problem. If you program the step rate for 4ns, then the ramp will span 22,500 steps (90us/4ns). To get the desired ramp, the 22,500 steps span the lower and upper frequencies, which determines the frequency step size: StepSize = (f_upper - f_lower)/22,500.
For a sawtooth, you probably want to set the "Digital ramp no-dwell high" bit, which causes the DRG to immediately return to the lower frequency after reaching upper frequency.
Controlling the PRF is a separate issue. Once you have programmed the ramp functionality, you can use the DRCTL pin to initiate a ramp sequence. The DRCTL pin effectively becomes your means for implementing the PRF.
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