I have successfully used the hdl_2016_r1 release of the HDL library to control the AD9361 on a Xiliinx UltraScale FPGA device. I have used the traiditional project-mode flow to generate bitstream files for the conventional and for the Tandem over PCIe (TPCIe) configuration method.
Now I would like to generate the bitstreams for the Tandem with Field Updates configuration method which uses Tcl scripts in the Vivado non-project mode to synthesize, place, route and generate the necessary bitstream files. But, I have run into a problem where the Vivado placer is failing to place the IDELAYCTRL primitive that is instantiaed in the ad_lvds_in.v source file. For some unknown reason, when called from a Tcl script in non-project mode, the place_design tool fails to place this primitive into one of the BITSLICE_CONTROL resources even though there are plenty of those available very closely located to the AD9361 rx_frame signal pins where this placement is currently failing.
Has anyone else had problems implementing the hdl_2016_r1 library in a UltraScale FPGA using the Vivado non-project mode? Right now the problem seems to be the IDELAYCTRL primitive but I suspect there may be more placement problems once this one is solved.
Any feedback and/or questions would be appreciated.