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ADV7611  read VIC

Question asked by jianghong on Jan 26, 2018
Latest reply on Jan 31, 2018 by Poornima

I just need the HDMI input signal,The configuration order is as follows:

  98 FF 80 ; I2C reset
  56 17 02 ; Encoder reset

 /*Sample new ALSB value for IO map */

   98 1B 01 ; Sample new ALSB value

   98  F4 80; // CEC

   98 F5 7C ; //INFORAME

   98 F8 4C; //DPLL

  98 F9 64 ; // KSV

  98 FA 6C ; //EDID

  98 FB 7C // HDMI

  98 FD 44 // CP

 There is a default configuration of 1080x50I,

/* Set VID_STD(IO Map 0x00[5:0]): 010100b=0x14 -> HD 1x1 -> 1920 x 1080 */

write_adv7611( fd, 0x98, 0x00, 0x14 ); 

/* Set VFREQ(IO Map 0x01[6:4]): 
write_adv7611( fd, 0x98 , 0x01, 0x15 );

 

write_adv7611( fd, 0x98, 0x02, 0xF4 );
write_adv7611( fd, 0x98, 0x03, 0x80 ); /* 16-bit ITU-656 SDR mode */
write_adv7611( fd, 0x98, 0x05, 0x2C ); /* AV Codes On */
write_adv7611( fd, 0x98, 0x06, 0xA6 );
write_adv7611( fd, 0x98, 0x0B, 0x44 ); /* Power up part */
write_adv7611( fd, 0x98, 0x0C, 0x42 ); /* Power up part */
write_adv7611( fd, 0x98, 0x14, 0x7F ); /* Max Drive Strength */
write_adv7611( fd, 0x98, 0x15, 0x80 ); /* Disable Tristate of Pins */
write_adv7611( fd, 0x98, 0x19, 0x83 ); /* LLC DLL phase */
write_adv7611( fd, 0x98, 0x33, 0x40 ); /* LLC DLL enable */

write_adv7611( fd, 0x98, 0xBA, 0x01 );  /* Set HDMI FreeRun */

 

write_adv7611( fd, l0x98, 0x9B, 0x03 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0xC1, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0xC2, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0xC3, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0xC4, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0xC5, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0xC6, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0xC7, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0xC8, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0xC9, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0xCA, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0xCB, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0xCC, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0x00, 0x00 ); /* Set HDMI Input Port A */
write_adv7611( fd, l0x98, 0x83, 0xFE ); /* Enable clock terminator */
write_adv7611( fd, l0x98, 0x6F, 0x0C ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0x85, 0x1F ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0x87, 0x70 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0x8D, 0x04 ); /* LFG */
write_adv7611( fd, l0x98, 0x8E, 0x1E ); /* HFG */
write_adv7611( fd, l0x98, 0x1A, 0x8A ); /* unmute audio */
write_adv7611( fd, l0x98, 0x57, 0xDA ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0x58, 0x01 ); /* ADI recommended setting */
write_adv7611( fd, l0x98, 0x03, 0x98 ); /* DIS_I2C_ZERO_COMPR */
write_adv7611( fd, l0x98, 0x75, 0x10 ); /* DDC drive strength */

 

After the aforementioned configuration, the VIC is read and the corresponding resolution setting based on the VIC:

HDMI input signal :1080ix50:

 

0x6f[0] = 1    cable: 

0x6a[4] = 1   hdmi clock:

0x04[1] = 1  pll lock:                        

0x05[7] = 1 HDMI

0x05[6] = 1 not HDCP encrypted

0x07[5] = 1 DE regeneration locked to incoming DE

 

0x44 0xB1[7] =  0 : Sync Channel 1 STDI measurements are not valid measurements
CH1_BL = 0x1fff

 

CH1_LCVS = 0 

 

CH1_LCF  = 0 

 

CH1_FCL = 0 
CH1_STDI_INTLCD 0x44 0xB2[6]  = 1 : Indicates a signal on Sync Channel 1 with interlaced timing

VIC :  20

 

HDMI input signal :1080Px60:

0x6f[0] = 1    cable: 

0x6a[4] = 1   hdmi clock:

0x04[1] = 1  pll lock:                        

0x05[7] = 0 DVI

0x05[6] = 1 not HDCP encrypted

0x07[5] = 1  DE regeneration locked to incoming DE
0x44 0xB1[7] =  0 : Sync Channel 1 STDI measurements are not valid measurements
CH1_BL = 0x1fff


CH1_BL  = 0 

CH1_LCVS  = 0

CH1_LCF =0

CH1_FCL = 0 
CH1_STDI_INTLCD 0x44 0xB2[6]  = 1 : Indicates a signal on Sync Channel 1 with interlaced timing

VIC : 0

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