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AD9689 Data Sheet, Rev A, page 101.  For Addr = 0x0111, clock superfine delay.  Third column says we get 8 bits [7:0].  However 128 delay steps only need 7 bits, 0x00 to 0x7F.   Setting column actually shows 129 steps.  Please clarify.  Thanks, John Reyla

Question asked by jreyland on Jan 25, 2018
Latest reply on Jan 30, 2018 by UmeshJ

AD9689 Data Sheet, Rev A, page 101.  For Addr = 0x0111, clock superfine delay.  Third column says we get 8 bits [7:0].  However 128 delay steps only need 7 bits, 0x00 to 0x7F.   Setting column actually shows 129 steps.  Please clarify.  Thanks, John Reyland

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