can I connect the sclk from an external master, not only to the slck input, but also the mclk of the ADAU1466? Just connect them in parallel to both? This to avoid having to run both EMI sensitive signals over the pcb
Yes, you can certainly do that. It has been done many time before.
Of course there are some important details:
1) the frequency needs to be in the correct range (I know that is an obvious one)
2) The BCLK output needs to appear early and never go away. When the part comes out of reset, or when powered up, it needs to see MCLK right away so the PLL will properly lock and so the initialization code will run. So even though it may have been powered up for a while, if there was no MCLK then the initialization procedures were not run until the MCLK was present. So you will need to wait a short time for this to happen before programming the part. Ideally, you should hold the part in reset until the rest of the system comes up. Then turn on the BCLK that feeds the MCLK input of the DSP and then bring it up out of reset. Then wait for a short time and then program the part. This info for the timing should be in the datasheet as I recall.
3) If the sampling rate changes thus that the BCLK output frequency changes then you might want to stop the DSP and disable the PLL then change the BCLK frequency and restart the PLL and the core.
4) Follow good signal integrity practices to prevent reflections from the split of this signal.
So these are my first thoughts knowing nothing of your application.
Excellent input Dave, thanks!
I am working on my first audio project, trying to keep things simple. I have I2S (master) in, to self boot DSP and stand alone DAC. no uP.
I am a bit puzzled with your point 3). Are the DSP and DAC meant to run at fixed master clocks - "ideally"? I sort of got the impression that the DSP and DAC internal clocks can scale along with the incoming sample rates. But a preferred restart suggests otherwise. Without a uP a restart is not possible I guess, so in that case i should have a separate MCLK running the DSP and DAC and use the ASRC in the DSP. Which is basically what the EVAL board for the 1466 is doing, but I was thikning it would make more sense to use the clock I get from the source instead. But this is related to the sample rate as you point out.
Regarding my point #3.
My point was that if you should have to change the actual MCLK frequency, then you should stop the PLL and relock it. This is simply to prevent the PLL from trying to lock to a rapid change in its reference frequency. So just keep that BCLK at the same rate.
In a "normal" system the MCLK is coming from some clock source and does not change. So the DAC and the DSP both will take this MCLK signal, go through a PLL to bump it up to a higher rate internally and then divide it down to develop the LRCLK and BCLK signals. So you are correct, that changing the sample rate can be as simple as changing the dividers and then it is running at a new rate. The MCLK stays the same. There are exceptions to this, if changing from a 48kHz rate to a 44.1kHz rate then either the MCLK has to change or the PLL has to be changed. So that is another entire topic. (The way to easily deal with this is to use an ASRC)
OK, so let's say you are running at 48kHz and are sending a TDM-8 signal to the DAC from the DSP. This means the BCLK will be 12.288MHz. Now if you change the sampling frequency settings in the DSP to be 96kHz then the BCLK now jumps to 24.576MHz. This is all fine if you then change the sampling rate of the DAC then all is good. However, you will be sending the BCLK not just to the DAC serial port, but to the DAC MCLK input! This is a sudden and significant change and you risk having the PLL latch up or all sorts of noise or garbage come out of the DACs. You then would have to change the settings of the DAC because some of the internal generated frequencies would be too high. So this is why if you change the sample rate of the port that is feeding the MCLK to the DAC you should shut down the PLL on the DAC, change the settings and restart the DAC.
The best way around this is to use a different serial port on the DSP to drive the MCLK to the DAC. But then you are back to what you were trying to do which was to reduce the high frequency runs on the PCB. Plus, then you probably would just use the CLKOUT pin of the DSP anyway.
So, if you use the BCLK from a serial port to drive the DAC serial port AND drive the MCLK , then if you change sampling rates you have to be careful and mute the DACs, shut down the PLL and restart it at the new frequency. Without doing this you could be OK sometimes, and sometimes you might get some noise and worst case you might lose all audio. The last is not likely but often times our customers must be certain this could never happen.
Your point is clear Dave, thanks. A sudden change to the MCLK / PLL is problematic, a change in BCLK is "what it is intended for"
But, I read in the AD1938 datasheet the following: the on-chip PLL can be selected to reference the input sample rate from the LRCLK pins. So perhaps this feature triggers an internal reset when a change in incoming sample rate is detected?
My source has the MCLK fixed as 256xFs, so not a stable clock. This does not make sense to me in light of your explanation.
We are bouncing around a little...
The PLL in the codec is designed to attempt to lock to any input signal within its range and we made a lot of effort to design it to not latch-up. So when it is locked and the input frequency changes more than the PLL can quickly adapt to then it unlocks, which will Mute the DACs, and then goes into a course lock mode to lock to the new frequency and then when it gets close it enters the fine mode and locks to the signal. Nothing in the codec changes as far as the dividers. It does not sense a new rate. As long as the ratio of MCLK to LRCLK and to BCLK stays the same then it will simple follow this new sampling rate. This is how you would change from 48K to 44.1K. None of the other dividers need to change. But if you were to change from 48kHz fs to 192kHz fs, without changing any of the dividers then the internal frequencies would be too high and the part would stop working. What would have to be done is to change the MCLK (MCS) setting to use 64 x fs instead of 256x fs. So my point to all this is you cannot just easily change the sampling rate of the codec to a drastically different rate without going into the codec and writing some registers.
So what is often done is to fix the codec sampling rate so the DSP to Codec communication would never change. Then use the sampling rate converters to convert to this rate. This is a great use of the DSP. You can use the master port to write the codec configuration when the DSP boots up. I recently tested this feature and documented some bugs and a work-around. So you do not have to use the codec in standalone mode. If you really need to change the codec rate then I think I could devise a way to do it from the DSP. I am not 100% certain of this so I would have to experiment. We have lots of new features added that I still have to explore to a greater depth.
Now, to the LRCLK feeding the PLL comments you made. This is just an adjustment to the allowable input frequency of the PLL so all what I said above still applies. Once it locks you should keep it stable if at all possible. Stable means that it does not stop and start and does not rapidly change. Jitter is another discussion. To use the LRCLK input to the PLL you have to use a different loop filter so there is a hardware change. You certainly can run in this manner but since both the LRCLK and the BCLK are off of the same port, then I would rather you use the BCLK. The codec also supports a BCLK-Less mode when all you send to the codec is LRCLK and data! No BCLK. This works fine at lower sampling rates but if you want to run at 96kHz or 192kHz the reality of PCB design and layout means there is a chance that you will experience clicks and pops from time to time due to timing errors. It is not the most robust way to run the codec. If you would choose to do this then PCB layout becomes REALLY important. In fact, when you start your layout get in contact with me so I could review it.
Now you said your source of MCLK is not stable? Why? Where is it coming from?
Thanks for the good input !
Just trying to understand:
So let's assume a fixed MCLK, so no changes to the PLL. How would a DAC then adapt to a change from 44.1 to 48kHz? Is this not possible, so a SRC is required?
Again with fixed MCLK, can a DAC "adjust" to a change from 48 to 96kHz sampling frequency? Does this require a uP to write a new divider to the register?
A very basic question: I assume I understand correct that the sampling rate into the BCLK is determined by the incoming audio signal which can be 44.1-192kHz for audio?
The source in my case is an Rx module with a MCLK = 256x sampling rate, which is therefore not fixed. Strange no?
These things would be much easier to ask over the phone. Is it possible to call you?
Just for clarity Dave, above I mean how would a DAC react to a change in BCLK from 44.1 to 48 and 48 to 96kHz, given a fixed MCLK.
I would also like to talk on the phone but you are in Denmark. I will inquire on how to do that. Is the phone number in your profile correct?
Changing the sampling rate from 44.1kHz to 48kHz will require the MCLK to be changed slightly. Again, fs x 256. However, the PLL will be able to follow it since it is not a huge change. You still should mute the audio before changing it. Now, changing from 48kHz to 96kHz will require register changes on both the DAC and the DSP.
If you are receiving audio from a transmitted source then you should use an ASRC since the Rx signal may come and go and will be drifting in frequency. We should talk... So much of these answers depend on the application and the desired features.
Can you call me on the number in my account? We can also skype if calling to DK is a problem. I have added my skypename to myanalog
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