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ADAU1466 'Paged' Address Mapping

Question asked by HayRoger on Jan 24, 2018

Sigma Studio V 3.16 Build 4. Device ADAU1466

 

I've noticed that all addresses in the export files are expressed terms of Slave Port mapped addresses. There appears to be no indication in the various export files which parameter addresses get mapped to the Lower and Upper pages. Running the design in Sigma Studio and monitoring the Slave SPI serial buss is one way of finding  which page the various parameters of the design are mapped to. Another other way is to study the 'Param Tab' in the Capture Window, which displays the parameters in terms of Core Addresses. Is there anyway of telling if an address is referring to lower or upper page based on the contents of the exported XML fie?

 

The in house developed tool chain that we use for product development makes extensive use of the Sigma Studio exported XML files. Our tool chain requires the address to be expresses as Core Addresses, not Slave Port paged mapping. The current exported XML format appears to contain no information as to if the address for a parameter is mapped to the lower or upper page. Hence, for us it would be very useful if the exports could be in terms of core addressing or an extra element added the XML, per address, that indicate the page that the address is referring to.

 

Our current work around is to use a small app we have written to add 0x5000 to the addresses that we have manually identified as belonging to the upper page. This process is prone to human error, especially when some of the DSP blocks, such as the Limiter, spread their parameter addresses across the lower and upper pages.

 

Roger H

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