I am looking at the interrupt latency of a 21584 chip for a simple rising edge signal on a DAI pin. I have mapped this to the DAI high priority interrupt and enabled that to interrupt the processor. In the very first instruction in the interrupt vector table, I raise flag 0. Comparing the rising edge interrupt signal to when flag 0 goes high, I see anywhere from 100-200 ns, or 50-100 clock cycles at 500 MHz. There are no other interrupts enabled in the system (other than emulator, reset, etc.).
That seems excessive to me, both in terms of the raw time and the >50 cycle variation. I know it has to push the status stack and flush the pipeline, but that seems like it would be on the order of 20 cycles and wouldn't have much variation.
Is this behavior expected? I have tried on an SC-58x as well and found it very similar. I stopped the other cores when testing this to remove interaction with other processors.