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JESD Framer doesn't send /K/ symbol in Lane1

Question asked by Andrew.Yen on Jan 24, 2018
Latest reply on Jan 25, 2018 by gverma

I'm using Mykonos C API to control AD9371 in a no-OS environment with a Altera Arria10 SOC platform.  After finishing initial calibration successfully, I enable AD9371 RxFramer and ObsRxFramer followed by local JESD reset in our FPGA.  The first strange phenomenon is that RxFramer or ObsRxFramer didn't send any /K/ symbol out to our JESD IP when the SYNC~ pin is set to low.   After I call a function to request AD9528 to send the SysRef signal out, I can then observe the /K/ symbol on Lane0 at the FPGA side.   However, the 2nd strange phenomenon is that I cannot observe the /K/ symbol on Lane1 to Lane3.  Please check the attached profile setting and the output result observed by "Signal Tap Logic Analyzer" in Quartus.  The signal jesd204_rx_pcs_data[0..63] in the module u9371_1 is the 1st JESD IP to get Lane0 and Lane1 from RxFramer while the signal jesd204_rx_pcs_data[0..63] in the module u9371_2 is the 2nd JESD IP to get Lane2 and Lane3 from ObsRxFramer.

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