I've a question about the frequency of the SPI clock to AD9371 EVB.
By checking the HDL projects downloaded from GitHub - analogdevicesinc/hdl: HDL libraries and projects, in the combination: AD9371 EVB + Altera Arria 10 SX (i.e., SoC) Dev. Kit, the frequency of the SPI clock generated by the SPI Master is only 128 KHz. This is the same if Arria 10 GX Dev. Kit is used instead.
However, according to our waveform measurement on board, in the combination: AD9371 EVB + Xilinx ZC706, the SPI clock rate is around 20 MHz.
Since AD9371's SPI slave supports SPI clock rate up to 50 MHz, we are trying to increase the SPI clock rate on Altera FPGA dev. kit.
Could you explain why the SPI clock rate is only 128 KHz on Altera FPGA dev. kit? Maybe ADI failed to increase it to higher frequency?