AnsweredAssumed Answered

AD9371&ZC706 init problem

Question asked by rosy2cloud on Jan 23, 2018
Latest reply on Jan 24, 2018 by rosy2cloud

Hi~engineers 

   I am using reference design of AD9371 on ZC706.the HDL version is 2016 r2,followed no-OS setup instruction,I have generated the bitstream and download it to FPGA.

when load customer profile in TES,configure information showed as below.Actually , it ' s a little different from the figure below ,in the device clock option, description words is "cus 245.76MHz"

ad9375 config

but when setup sdk dedug,it shows a error information 

"xcvr_calc_cpll_settings:failed to find matching dividers for 9830400 KHz rate" showed in the picture below.error info

 

it seems like clock config error,but it's sure the config is right on version "2016_R2-2017_06_29.img".so How to solve the problem?

     thanks.

Outcomes