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AD9548 output clock not stable

Question asked by Ajay_Bitmapper on Jan 23, 2018

We are doing the AD9548 configuration using VHDL on FPGA Kintex 7 .Actually we are getting output but output is not being locked properly. These are our specifications,

  • Reference input = 1 PPS
  • Desired output = 250 MHz
  • Input = 20 MHz (Low frequency input)

I have also attached the output signal images and the register settings. Also we are not getting adject 250 MHz instead we are getting some 227.3 MHZ .Please look it and provide some solution to it. Thanks in advance.