- I'm considering using the ADuCM329 for an ultralow power application that requires a slow sampling rate of 500Sps, I believe the documentation says single channel single conversion is possible but for SPS lower than 10Ksps dummy conversions are needed (at a 100us delay max). This dummy conversions have to be the full ADC working or could they just reading the ADC output data register (or memory address)? I mean do I actually have to set the ADC_CNV_CFG.SINGLE bit with a maximum delay of 100us?
- What is the capacitance of the sampling circuit of the ADC? Do you have an equivalent circuit diagram so that I can estimate the required characteristics of an external buffer and the sampling time? I can't seem to find this information anywhere.
- After the sampling phase of the ADC how much does the conversion phase last? Is there a rough estimate in terms of PCLK or ADCLK cycles?
- The current estimation in the datasheet says that for a 100KSps and 1KHz input signal the current consumption is 104uA (with 1.8 supply) through VBAT_ADC while the ADC is doing a conversion. Is this the current in the "sampling + conversion phase" only or is it a mean consumption in those conditions?