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AD9361, High RF DC OFFSET

Question asked by Shay.L on Jan 22, 2018
Latest reply on Mar 17, 2018 by Jerry_loo

Hello,

I am working with the AD9361 in FDD state, LVDS mode at 3.XGHz connected to our board.

Type of signal 5MHz, 10MHz and 20MHz LTE signal.

At Rx plot (after FFT [at frequency domain]) I can see that the RF DC OFFSET is very high.

At the beginning I thought that this is LO leakage problem.

 

I stopped all the RF sources inside the RFIC:

I wrote Register 0x015 = 0x64, Power down the Tx and Rx synthesizers.

I wrote Register 0x050 = 0x02, Power down the Rx synthesizer VCO.

I wrote Register 0x051 = 0x02, Power down the Tx synthesizer VCO.

At Rx plot (after FFT [at frequency domain]) I saw that the RF DC OFFSET was very high. And I assumed that something else is causing the high RF DC OFFSET.

 

I changed registers 0x054 and 0x055 to 0xFF (ADC OFF) and measured the Rx path DC complex value using FFT (time domain).  I got (-1-j1)

 

I also have an EVB from Analog Devices (AD9361 R2 Board number: 7140)
This board is working at CMOS mode.

I changed registers 0x054 and 0x055 to 0xFF (ADC OFF) and measured the EVB Rx path DC complex value using FFT (time domain).  I got (0+j0). 

 

This (-1-j1) offset is causing my RF DC OFFSET problem.

1.  Why in LVDS mode when the ADC are at OFF state I measure Rx path DC complex value of (-1-j1) and on the EVB I measure Rx path DC complex value of (0+j0) ?   What is causing this offset ?

 

Thanks,

Shay.

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