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FMCDAQ2 RX Number of Lanes (2 instead 4)

Question asked by cerasic on Jan 22, 2018
Latest reply on Jan 25, 2018 by cerasic

Hi all,


I'm still stucking to find a solution to increase the DAC sample rate.
I use FMCDAQ2 R2017_R1 hdl and No-OS
{pls see Other Post FMCDAQ2 USING DACPLL
FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz


The issue  seems  simple:
  my configuration  ADC 300Mhz & DAC 600Mhz  (My design is limited to 333 Mhz)
  I want just to increase the DAC sampling (for instance:  1Ghz or 1.2Ghz)
  I use only DDS mode
 First Trial: I used DACPLL (AD9144) :
        PLL AD9523 frequency is 4ghz/6    = 666 Mhz  (vco_diff_m1=5)
         ADC clock   666Mhz/2
         DAC clock = 1 Ghz comes from DACPLL that's driven by  reference clock 666Mhz from AD2523    
         DAC FPGA clock = 666 Mhz/4   becomes a problem ?     
        I wanted to ignore TX JESD204B, NO WAY,  because the DDS information comes through
         JESD204B  (the DDS setting in dac_core about phase, frequency, scaling)


Second Trial :
           Try   ADC 250Mhz & DAC 1000Mhz, and use only 2 Lanes  for RX JESD204B (to overcome the min. Lane rate)
           instead   m=2, l=4, f= 1  I use  m=2, l=2, f= 2
           it runs  without  error messages, no lock issue,  but no data is captured  (only zeros are captured) any suggestions to check ?
My question:  is it possible to set 2 lanes in the sofware AD9680 Reg 0x570 
[see     ad9680_spi_write(dev, AD9680_REG_JESD204B_QUICK_CONFIG, 0x49);    // m=2, l=2, f= 2
  without changing the Hardware ?
 Thank you for your help
             Kind Regards