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AD5592R: Configuration 2xADC and 1xDAC: Intermittent ADC Data Channel swaps on SPI Bus

Question asked by Patch-3153 on Jan 21, 2018
Latest reply on Feb 1, 2018 by Patch-3153

Hi AD, We're using the AD5592R Integrated ADC/DAC within our system in a configuration with two ADC Channels (IO0, IO1) and one DAC Channel (IO2) and are seeing intermittent ADC Data Channel swaps (and ADC Conversion errors) on the read data from the SPI Bus.


The errant behaviour is consistent following system startup, although we have seen some systems demonstrate both normal ADC Channel behaviour and errant behaviour on sequential startups. In addition, the errant behaviour is only seen on a small percentage of our systems.


We have determined that our startup sequence uses an incorrect reset code (0x7DDC instead of 0x7DAC) and three of the IO Pins (IO3 ~ IO5) are not set to a defined state using the Pin Configuration Registers.


Could you please confirm whether these startup sequence items (or other known issues) could be contributing to the channel swap behaviour we are observing?


Thank you for your follow up and guidance.
Best regards,