I am able to acquire proper reading after 3 conversion cycles. Can anybody please explain me, whether this ADC behaviour is common or i am making some mistake .
i am using external VREF of 2.048V
VCC = 3.3V
From power-up, in any read/write mode, the AD7682 first three conversion results are undefined because a valid CFG does not take
place until the 2nd EOC; thus two dummy conversions are required. Also, if the state machine writes the CFG during the
power-up state, the CFG register needs to be rewritten again at the next phase.
Retrieving data ...