I have a question about HSC-ADC-EVALCZ board.
The question is that is there no problem without using sram code?
because I have this board that have no ram on this board.
There is no need for SRAM as long as the software (VisualAnalog) is set to capture 64k samples. The FPGA's internal memory will do the data buffering.
Moved to High-Speed ADCs.
Retrieving data ...