We are evaluating using the AD9371 for our application and I have run into some confusion about what clock signals I am going to be required to generate to get the maximum data rates. We are purchasing the ADRV9371 eval board for our prototyping, the user manual for the eval board states to provide a 30.72MHz clock for the REF CLK signal, this seems to drive the AD9528 to generate the other required clocks for the AD9371. Is the 30.72MHz reference the only clock signal I need to generate for maximum data rates? The datasheet for the AD9371 is a bit confusing to me as it states you can provide any clock from 10MHz-320MHz but am I correct in assuming that for maximum data rates you have to provide the 320MHz, i.e. you cant just provide 10MHz to the AD9371 and its internal PLL and synthesizer generate any required clock for maximum data rates?