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question about ad9371 hdl reference design in Tx chain

Question asked by rosy2cloud on Jan 18, 2018
Latest reply on Jan 19, 2018 by CsomI


   I am using  adrv9371 hdl reference design on zc706, I want to add a ram and  own module before ipcore "axi_ad9371_dacfifo" to verify algorithm, and the ram can circulately send signal through own module to "axi_ad9371_dacfifo".but I get confused with ipcore "axi_ad9371_tx_dma",the output "m_axis_data" is 128 bit,and It looks like consist of Tx1_i/q and Tx2_i/q, but what is the relation between  "m_axis_data" and Tx1_i/q,Tx2_i/q?