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Regarding AD9208 JESD204b configuration parameters

Question asked by anh on Jan 17, 2018
Latest reply on Jan 17, 2018 by UmeshJ

Hi  Everyone,

 

I am  currently using the AD9208-3000EBZ which is interfaced with VCU118 (Virtex Ultrascale +) board.

 

I need to use both ADC cores (ADC_0 and ADC_1) on the AD9208 chip. Each core needs to operate at 3GSPS.

 

When I look at the schematics of the VCU118 boards and AD9208 boards, I saw that the 8 serial JESD204b output lanes DOUT[0:7] from the the AD9208-3000EBZ board are routed to two non-adjacent quads on the VCU118 boards (GTY121 and GTY126 quads;  DOUT[0:3] is routed to the quad GTY121 and DOUT[4:7] is routed to the quad GTY126).

 

Because the quads are not adjacent to each other, they can not share the same reference clock.  Therefore, in order to reliably transfer the ADC samples into the FPGA fabric, I need to place  ADC_0 core's samples into lanes 0 to 3 (DOUT[0:3]) and ADC_1 core's samples into lanes DOUT[4:7]. Using this approach, the samples from each core only go to one quad and the we will not  any issue related to different reference clocks. I am also not using any DDC (Digital Down Converter) on the AD9208 chip.

 

My question is how do i configure the AD9208 chip to make ADC_0 core samples go to lanes 0 to 3, and to make ADC_1 core samples got to lanes 4 to 7 ?

 

I am thinking to set the parameters like this: L = 4, M = 1, F = 2 ? But  I am still not sure if my thought is correct. Or Do I have to set  other parameters as well?

 

Also, it would be very much appreciated if  you  can share with me any C or C++ example codes to do AD9208 or AD9689 SPI configuration.

 

Thank you very much for your kind help and support.

 

Regards,

 

Anh

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