I would appreciate clarification for B and LR clocks for the ADAU1467.
The system we have under design has 4 TDM8 streams input on each of the input lines, and 4 TDM8 streams outputs on each of the output lines. The MCLK signal is fed in from another source.
We want to set up the ADAU1467 as the master to output aligned LRCLCKs and BCLCKs to the other codecs in the system and to align all of the inputs and outputs of the ADAU1467.
Would the setting be corrects if we set up the serial ports in SigmaStudio, as follows:
Serial input Port 0 fields BCLK and LRCLK to master
Serial input ports 2,3, and 4 as slaves to CLK domain 0
All serial output ports including port as slaves to CLK domain 0