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ADV7511 Embedded Sync Issues

Question asked by georgr on Jan 12, 2018
Latest reply on Feb 2, 2018 by georgr

Hi everyone

I have been working on making the ADV7511 on the ZEDboard work with my own HDL modules, configuring it with the ARM core running bare-metal software.

I have been able to get SDR/DDR 4:2:2 inputs on ADV data pins 23:8 (modes 1/6) to work fine with separate syncs and would like to implement embedded syncs next with modes 2/8 (SDR/DDR respectively). I have designed my core such that the embedded sync words (FF, 00, 00, SAV/EAV) are inserted on both the luma and chroma channel in parallel (as it is done in the ADI Reference design module axi_hdmi_tx_es). This means that transmitting the 4 EAV/SAV words takes 4 pixel clock periods. To configure the DE/Sync generation, I referenced tables 33-35 of the programming guide for the format I am using (CEA861 VIC4/720p60), with 0x17[0] and 0x41[1] both set to 1. However, this results in the following symptoms:

-in SDR mode (Inp. ID 2, right justified) the displayed image has distorted colors - black and white are mapped to a spectrum of dark to bright blue. Artifacts resulting from JPEG compression (I am displaying a tiled test image which is stored in an FPGA block RAM) are very pronounced and appear in different colors.

-in DDR mode (Inp. ID 8) I am not getting any picture at all.

In both cases, reading 0x3E (detected VIC) yields the correct format ID (4) which I am trying to display.


What could be causing this? Am I misunderstanding how to place the embedded sync words?


Another related question I have is regarding the Sync Adjustment/DE generation:

Is my approach (enabling both sync adjustment and DE generation) correct? If so, why are they even needed - from what I can understand, the embedded sync decoder will generate DE and use 0x30-0x34 to determine H/VSync placement relative to that? The programming manual is not entirely clear on this, but figure 6 on page 53 of the programming guide does show a mux for the source of the "baseline" DE/Sync signals with a table that indicates that using input ID 2, the embedded sync decoder is not used (which leaves me wondering where else it would get any syncs etc. to adjust in the first place?) - a similar question has been asked at ADV7511 DE,Sync Generation but was ultimately left open.


Thank you very much and best regards

Georg Rutishauser