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ADV748x TXA/TXB undocumented bit

Question asked by kbingham on Jan 13, 2018
Latest reply on Jun 19, 2018 by PoornimaSubramani

Hi All,


I have up-streamed the ADV748x driver (supporting the ADV7480, ADV7481, and ADV7482) to the Linux Kernel.


The prototype code (not written by me) had the following code to handle TXA/TXB lane power:

static int adv7482_txb_power(struct adv7482_state *state, bool on)
       int val, ret;

       val = txb_read(state, 0x1e);
       if (val < 0)
               return val;

       if (on && ((val & 0x40) == 0))
               ret = adv7482_write_regs(state, adv7482_power_up_txb_1lane);
               ret = adv7482_write_regs(state, adv7482_power_down_txb_1lane);

       return ret;

The only datasheet I have to describe the registers is  ADV7481_UG-747.pdf, and it does not detail the BIT(6) at register 0x1e on TXA or TXB.


As such I converted this code to :

int adv748x_txb_power(struct adv748x_state *state, bool on)
    int val;

    val = txb_read(state, ADV748X_CSI_FS_AS_LS);
    if (val < 0)
        return val;

     * This test against BIT(6) is not documented by the datasheet, but was
     * specified in the downstream driver.
     * Track with a WARN_ONCE to determine if it is ever set by HW.
    WARN_ONCE((on && val & ADV748X_CSI_FS_AS_LS_UNKNOWN),
            "Enabling with unknown bit set");

    if (on)
        return adv748x_write_regs(state, adv748x_power_up_txb_1lane);

    return adv748x_write_regs(state, adv748x_power_down_txb_1lane);

Now of course I have a report that the BIT6 is set while trying to turn on the TXB lanes.


This bit is also set in the register tables which are described as an 'ADI Required Write'

static const struct adv748x_reg_value adv748x_power_up_txb_1lane[] = {

    {ADV748X_PAGE_TXB, 0x00, 0x81},    /* Enable 1-lane MIPI */
    {ADV748X_PAGE_TXB, 0x00, 0xa1},    /* Set Auto DPHY Timing */

    {ADV748X_PAGE_TXB, 0x31, 0x82},    /* ADI Required Write */
    {ADV748X_PAGE_TXB, 0x1e, 0x40},    /* ADI Required Write */
    {ADV748X_PAGE_TXB, 0xda, 0x01},    /* i2c_mipi_pll_en - 1'b1 */
    {ADV748X_PAGE_WAIT, 0x00, 0x02},/* delay 2 */
    {ADV748X_PAGE_TXB, 0x00, 0x21 },/* Power-up CSI-TX */
    {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */
    {ADV748X_PAGE_TXB, 0xc1, 0x2b},    /* ADI Required Write */
    {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */
    {ADV748X_PAGE_TXB, 0x31, 0x80},    /* ADI Required Write */

    {ADV748X_PAGE_EOR, 0xff, 0xff}    /* End of register table */

The source of these 'required writes' looks likely to have come from the file:



which describes this bit in section 9.5.1 as part of the Power Up Sequence:

   (step 5. Set register 0x1E[6:5] in the CSI Tx map to 0b10.)


while the file ADV748x_Recommended_Settings_PrA_2014-08-20.pdf makes no reference to this bit except to set it to 0x00 on power down.


Because the code sets this as part of the power_up_txb_1lane registers, I can assume that the reason for my WARN_ONCE being fired is that the lane is powered on already - but I do not currently know if this is a valid status bit that is being read from the hardware.


Before I make any wild assumptions about a magic undocumented bit, Is there anyone that has access to identify if this is a valid status bit ? or the true purpose of TXA/TXB: 0x1e BIT(6) on either the ADV7480, ADV7481, or ADV7482?




Kieran Bingham