I'm currently working on a project that requires output from multiple phase-locked AD9914 with FM at an update rate of 100 MSPS.
I am using AD9914 evaluation boards with a 50 MHz clock generated on an FPGA and a frequency multiplier of 48 to obtain a core clock frequency of 2.4 GHz. Configuration of the DDS using SPI is successful and the SYNC clk output is at 100 MHz, as expected.
My first question is about the SYNC clk output. The datasheet specifies a rise time of 0.65 ns and a duty cycle of 45-55%. When looking at this output using a 500 Ohm resistor into the 50 Ohm terminated input of a scope (1 GHz BW), I find a rise time of ~1.5 ns and a duty cycle of 33%. Is this a typo in the datasheet?
Beyond this, I am having trouble with signal integrity using the evaluation board. In a nutshell, I see reflections on signals to/from the DDS. All connections are as short as possible, using either coax cable (RG174) or twisted pair. Are others using evaluation boards in this way without trouble? Is there a documented example of direct mode working @ 100 MSPS on the evaluation boards? If so, should source termination or external buffers be used to warrant SI?
The final question I have is about the SYNC circuitry. If I'm already using an FPGA, is it recommended to use it for SYNC OUT buffering and distribution? Are there documented requirements available on the skew, delay and jitter of the SYNC signals?
I believe to recall that documentation of multi-chip synchronization was removed from the AD9914 datasheet, but this functionality is available on them and not just on the AD9915, correct? I'd much rather use the AD9914 despite the higher price (eval boards are the same price anyways) because the clock divider of 24 (rather than 16 on the AD9915) gives me a nice 100 MHz timebase that is locked to the DDS when it's operating at 2.4 GHz core clock frequency.
Any help is appreciated!