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AD9635 Clocking

Question asked by BCAO on Jan 11, 2018
Latest reply on Jan 16, 2018 by pkern

The clock for an AD9635 is from an FPGA PLL in LVDS. In this case, can I directly connect the PLL clock outputs to the clock inputs of AD9635 with capacitors and resistors without using a clock buffer such as AD951x in Fig 60 on page 22  of AD9635 data sheets? Many thanks.