I'm targetting an application that must generate a chirp with very low phase noise with AD9910.
I'm far to achieve the target performance and I was wondering if I am misunderstanding the plot of the residual noise of the datasheet.
I'm performing several test to validate the phase noise outcoming from the DDS.
My test configuration is as follows:
- External XO with very low phase noise at 50 MHz
- Evaluation board of the DDS with PLL enabled and multiplier equal to 20 (clock 1 GHz).
- Tone mode to generate 99 MHz output
It is known the the phase noise resulting from the DDS strictly depends on the XO used to drive it, which is not considered in the residual phase noise plot of the DDS. My question is: when using the PLL+VCO the resulting clock phase noise is dominated by the its phase noise (ADF4106 with phase noise of about -90 dBc/Hz when used to generate 900 MHz, as plot in the datasheet)? This means that the output tone at 99 MHz can never have a phase noise lower than 110 dBc/Hz (factor 1000 MHz/99MHz= between clock and output RF which implies phase noise scaling of 20 dB), no matter how good is the XO used. Is this correct?
In this case the plot of the residual phase noise of the datasheet when using the PLL are not significant.
single tone with very low phase noise.
Thank you very much for your valuable time and attention.