Hi, I'm trying to understand the Short Transport Layer (STPL) Testing for the AD9164. As far as I can tell, I'm following the directions in the AD9164 datasheet, under "Transport Layer Testing", but when I check the SHORT_TPL_FAIL register at the end of the test, the result is always 0 (indicating a pass), even when I force a failing condition.
My JESD configuration is L=8, M=2, F=1, S=2. I confirm that the DAC has accepted these and achieved sync through register reads.
Here is the process I'm following:
Per steps 1 and 2, I start by establishing link and then setting my JESD transmitter (in an FPGA), to send a constant repeating set of 16 samples: A5B4, FFFF, FFFF, FFFF (repeated 4 times)
Step 3: I next set DAC Register 0x32E = 0xCC and Register 0x32D = 0xDD, which should tell the DAC that to expect a sample with a value of CCDD (which is deliberately wrong)
Step 4-6: I then follow the next steps to select sample 0 of DAC 0, enable the test, and reset the test:
Register 0x32C = 0x00 # select sample 0, DAC 0
Register 0x32C = 0x01 # enable test mode
Register 0x32C = 0x03 # reset
Register 0x32C = 0x01 # remove reset
Step 7: I then wait 10 seconds and then set register 0x32C = 0x0 to end the test.
Step 8: When I then read register 0x32F (SHORT_TPL_FAIL) I always get a value of 0x0, indicating a pass. I've tried this with multiple value for the expected sample and for the values sent from my transmitter in the FPGA, and the result is always 0 (passing).
Is there anything I'm doing wrong or interpreting wrong? I'd like to run this test as a double check that I'm formatting the sample data correctly.