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AD9371 hdl_2017_r1 JESD cores configuration

Question asked by zsami on Jan 10, 2018
Latest reply on Jan 20, 2018 by zsami

Hi, 

I'm using the ad9371 evaluation board with a zinq zc706, I'm building an application (no-OS) using the hdl and sw from github 2017_r1 branch. I know this branch is still under development, still I tried to make it work. I guess there is a problem with JESD cores getting properly reset. Besides, rx_phy0, rx_phy1  inputs to rx_jesd core is 64 bits instead of 32 bit, assuming default configuration of 2 lanes for the rx channels. I had to implement JESD cores outside of the block design using static configs and verilog codes provided in the library folder. It works but it's not reliable. I mean there is no error while running the application but sometimes the received signal does not make sense. Is there any thing else other than static configs that I should take into account to implement Jesd cored outside of the block design without needing them to be configured through sdk (axi_jesd)?

 

Thank you in advance.

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