We have troubles when we connected AD9250-FMC-250EBZ with HSC-ADC-EVALEZ:
1, Following the QuickStart Document, in VisualAnalog, we select AD9250 Average FFT; but the SPIController can't access the AD9250, it seems the VisualAnalog select the wrong MCS FPGA file: ad9250_evaldz.mcs.
2, Then we manually select another MCS FPGA file: ad9250_evalez.mcs, the SPIController can access the AD9250, but still can't capture data, it reports error: The number of converters in the ADC settings  need to match the number of headers selected ;
3, Then we removed Ch.B Output Data at ADC Data Capture Settings; it still report error: Read cannot be performed because FIFO is not ready for readback. We check the clocks from AD9250 board to Data Capture Board: FPGA_GLBCLK_P/N and GBTCLK0_P/N; They are all ok, and have the same 50Mhz frequency as the CLKIN_P/N input of AD9250.
We download ad9250_evalez.mcs from this page: EVALUATING THE AD9250/AD6673 ANALOG-TO-DIGITAL CONVERTERS [Analog Devices Wiki]
We highly doubt about the MCS file at this page have some mistake.
Whether a higher version of VisualAnalog can auto select a correction MCS file for AD9250-FMC-250EBZ, or is there any other MCS file we can get. And Can you send us the FPGA design source code for AD9250-FMC-250EBZ with HSC-ADC-EVALEZ?
VisualAnalog version: 126.96.36.199
SPIController version: 188.8.131.52