I'm trying to use the SPIDIV register to set the SPICLK frequency on my ADuC7122, and I'm seeing unexpected behavior.
At SPIDIV = 1, 7, and 63, the clock looks approximately like I'd expect based on the datasheet:
But at SPIDIV = 127, I see almost exactly the same output as at 63:
And then at SPIDIV = 199, I actually see SPICLK frequency increase. It looks suspiciously like the output at SPIDIV = 7:
The datasheet describes SPIDIV as an 8-bit MMR, but it almost looks like the ADuC7122 isn't honoring the top two MSBs. Is there an undocumented limit on this clock divisor? If so, what is it? If not, what's going on?