I have been using AXI_DMAC IP for both RX/TX in PicoZed Zynq. For our custom interface that I am making, I'd like to use AXI_DMAC to move data from PL to PS, but with more autonomy that it's designed for.
Currently the DMA descriptors are programmed by SW via an axi_lite interface. Since I need to send packets to PS from PL where SW has no knowledge of arrival and length of it, I wonder if I can connect another M_AXI_LITE to AXI_DMAC in the PL and configure the descriptors the way it was supposed to be configured by SW? Theoretically I don't see any problem with this approach, but please let me if you see any concern for this method.