I am using a FMCDAQ2-EBZ eval board on a KCU105 FPGA board.
Everything works fine expect the AD9144 which output stays at 0.
All PLLs are locked, SYSREF has been captured (reg 0x03B reads 0xD), no JESD204B configuration error, ILA received link informations are correct, and the PHY PRBS test is successful.
TxEN is high (measured on board with a multimeter), sync logic is not busy (reg 0x03B reads 0xD and sync is configured in one-shot mode), but the BSM (blanking state machine) still holds the output data at midscale: reg 0x147 reads 0x00.
Using the ADI code with no modification for the FMADAQ2 and the AD9144 on my FPGA design does not work either.
Using the reference design provided with the AES-KCU-JESD kit and ADI IIO Oscilloscope, the output is ok, so the DAC is not faulty.
Using ADI IIO I captured the registers values and compared them to the registers values from my design in the attached file. The only differences are the JESD operating mode (mode 2 instead of mode 5), the use of the DAC PLL, the updated datasheet values for the DAC & SERDES PLL configuration, and the blanking state machine.
Are there any other conditions that could cause the BSM to hold the output data at midscale?
I looked at these two posts, with no solution: