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FMCDAQ2 USING DACPLL

Question asked by cerasic on Jan 9, 2018
Latest reply on Jan 9, 2018 by cerasic

Hi All,

 

I 'm on FMCDAQ2 + K705 FPGA Release R2017_R1 hdl and No-OS software,

 

I using the configuration  ADC 300Mhz and DAC 600Mhz,  both sampling clocks are driven by the AD9523 PLL.

so I have this setting in the main function fmcdaq2.c

 

            printf ("5 - ADC  300 MSPS; DAC  600 MSPS\n\r");
            p_ad9523_param->pll2_vco_diff_m1 = 5;
            (&p_ad9523_param->channels[DAC_FPGA_CLK])->channel_divider = 4;
            (&p_ad9523_param->channels[DAC_DEVICE_CLK])->channel_divider = 1;            //  DAC CLK 600 Mhz
            (&p_ad9523_param->channels[DAC_DEVICE_SYSREF])->channel_divider = 128;
            (&p_ad9523_param->channels[DAC_FPGA_SYSREF])->channel_divider = 128;
            (&p_ad9523_param->channels[ADC_FPGA_CLK])->channel_divider = 4;            // ADC CLK 300 Mhz
            (&p_ad9523_param->channels[ADC_DEVICE_CLK])->channel_divider = 2;
            (&p_ad9523_param->channels[ADC_DEVICE_SYSREF])->channel_divider = 256;
            (&p_ad9523_param->channels[ADC_FPGA_SYSREF])->channel_divider = 256;
            p_ad9144_xcvr->reconfig_bypass = 0;
            p_ad9144_param->lane_rate_kbps = 6000000;
            p_ad9144_xcvr->lane_rate_kbps = 6000000;
            p_ad9144_xcvr->ref_clock_khz = 150000;
            p_ad9680_xcvr->reconfig_bypass = 0;
            p_ad9680_param->lane_rate_kbps = 3000000;
            p_ad9680_xcvr->lane_rate_kbps = 3000000;
            p_ad9680_xcvr->ref_clock_khz = 150000;
            p_ad9144_xcvr->dev.lpm_enable = 0;
            p_ad9144_xcvr->dev.qpll_enable = 0;
            p_ad9144_xcvr->dev.out_clk_sel = 3;
            p_ad9680_xcvr->dev.lpm_enable = 1;
            p_ad9680_xcvr->dev.qpll_enable = 0;
            p_ad9680_xcvr->dev.out_clk_sel = 4;   

 

Now I would like to use the internal dacpll in order to sample the DAC with 1.2 Ghz clock. The 600 Mhz is kept as reference clock for the dac PLL, see the below schematic of the AD9144

 

 

What should I change in those parameters :

 

            p_ad9144_xcvr->reconfig_bypass = 0;
            p_ad9144_param->lane_rate_kbps = 6000000;
            p_ad9144_xcvr->lane_rate_kbps = 6000000;
            p_ad9144_xcvr->ref_clock_khz = 150000;

            p_ad9144_xcvr->dev.lpm_enable = 0;
            p_ad9144_xcvr->dev.qpll_enable = 0;
            p_ad9144_xcvr->dev.out_clk_sel = 3;

 

I guess Lane rate   p_ad9144_param->lane_rate_kbps = 2*6000000 

what about the parameters ?

 

Is the portion of fmcdaq2.c  :

       // set up the XCVRs
    if (ad9144_xcvr.dev.qpll_enable) {    // DAC_XCVR controls the QPLL reset
        xcvr_setup(&ad9144_xcvr);
        xcvr_setup(&ad9680_xcvr);    
    } else {                // ADC_XCVR controls the CPLL reset
        xcvr_setup(&ad9680_xcvr);
        xcvr_setup(&ad9144_xcvr);
    }

Still Valid.

 

I have to mention I want just using DDS mode, which means the DAC doesn't need to receive data from FPGA,

But I want the ADC XCVR works fine, when I did this trial the ad9144_setup PLL won't look, and no data was available

on the capture.

 

Thanks a lot for your help

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