I am using a Adau1450 with three I²S inputs and three I²S outputs. Output0 is master of BCLK and LRCLK and should generate a LRCLK of 93750Hz. For two channels, BCLK should be 93750*32*2 = 6Mhz
The DSP is clocked on MCLK with 24.0MHz. I attached an example file (lend from Dave Thib: "ADAU 1450 I2S and GPIO output issues ") what I changed a bit to set the proper outputs and enabling only CLCKGEN1. PLL devider is set to 8 (PLL input frequency=3.0Mhz), PLL FEEDBACK DIVIDER is set to 98 (PLL output is 98*3=294/2=147MHz). According to my calculations, I need to set M to 49, N to 32 in order to generate a BCLK of 6Mhz ( (147MHz/1024)*32/49)=93750. But all what I get is a BCLK of 9.18Mhz. I get around 6Mhz when I change M to 98
Does anyone see my flaw? What I also found is, that the BCLK only changes when M is about 3 times N. If that condition is not met, BCLK is 9.18MHz. When M is larger than (3*N), I can reduce BCLK to, for example, 6MHz...
Oh, I'm using SigmaSudio version 3.15, Build 2, Rev 1721
Hope someone can point me in the right direction :-)
With kind regards,