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AD-FMCDAQ2-EBZ HDL Design DMA

Question asked by AraAdamian on Jan 8, 2018
Latest reply on Jan 29, 2018 by AraAdamian

We are working with the provided HDL design for the AD-FMCDAQ2-EBZ with the ZC706 platform. We are trying to write PS code to grab all the analog input data through the AD provided AXI_9690_FIFO IP block and are having issues. Could anybody explain this block, or how the data is passed up from the ADC to the PS, in general?

 

We get the data is packed with 4 samples per channel, with two channels worth of data (128 bits total) as it goes into this block. What we don't understand is what goes on this FIFO block to buffer the data. Since the data exists the block at 64bits @ 100MHz, clearly its only a matter of time till the FIFO fills up.

 

Did AD intend for the FIFO block to only store however much data can fit into the FIFO (i.e. not use it to "stream" adc data but to only capture periodic "frames")? Does the FIFO use the PL DDR3 as the storage space?

 

Any help understanding the intended PS application to work with this DMA block would be appreciated.

 

Thanks!

Ara

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