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Subthreshold MOS modelling in SPICE

Question asked by romanfragasse on Jan 8, 2018
Latest reply on Jan 16, 2018 by AnneM
Hi All,
 
I am in need of a discrete NMOS with subthreshold currents operating down in the pA region, and a corresponding model that I can compare characterization data to. My team and I are attempting to operate a discrete MOSFET deep into the subthreshold region for a proof of concept design that will eventually be integrated.  To this point, we have used an N Channel FET from a different supplier and have been able to measure subthreshold currents in the 10s of pA range. However, when trying achieve those results in simulation with the corresponding model file, we are only able to get results in the uA range or higher for the same bias voltages as in our test setup. The model we have used from the other supplier is a level 3 SPICE model, which poorly models the subthreshold region. In a typical application, this would be OK since these FETs are typically not operated in this region, but for our proof of concept design this is inherently critical. 
What I would like to know is the following:
1.) What level of SPICE models do you typically create for your discrete FETs. 
2.) Do you have anything in your portfolio of products that meets the 10s of pA subthreshold performance, and also has an accompanying model? 
If the second question requires me to make a second post please ignore it. My main interest here is the complexity of the SPICE models that ADI offers for their discrete FETs and similar product families. Thanks in advance,
Roman Fragasse

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