Rockwell Collins, Inc, January 7, 2018
Do you think the following this will work for interleaving four AD9689s please?
Figure below shows first two ADCs of an interleaved four ADC design. ADC0 samples at 0deg and ADC1 samples at 90deg. Clk1 is 90 deg delayed from Clk0. ADC0 gets SysRef (SDClk0) aligned with Clk0.
Clk1 retimes SDClk0 to make a SysRef aligned with Clk1.
Here is the corresponding timing diagram: