I load my board design into Hyperlynx and am trying to simulate the LVDS input being driven by a Smart Fusion 2 FPGA in LVDS mode. I have found out that the AD9361 IBIS model does not have the 100 ohm termination in the Model. The model only has a separate input buffers for the P and N polarities instead of a differential input LVDS buffer. The TX data input has the 100ohm termination in the part but not sure how I can simulate this termination.. How is this termination implemented in the actual Part? How is the differential signal handled in the part?