About T2CLRI Register,
It is described as follows in ADuC7023-datasheetP88.
"The user must perform successive writes to this register to ensure resetting the timeout period."
Does "successive writes" mean continuous writing?
Please let us know about the conditions to end continuous writing(successive writes).
(For example, until T2VAL matches T2LD, etc.)
About ARM REGISTERS,
It is described as follows in ADuC7023-datasheetP21.
"Each operating mode has dedicated banked registers."
Specifically, which register is "banked registers"?
Do "banked registers" refer to the gray registers listed in Figure 15. Register Organization?
In FIQ mode, can we understand that only "R8_FIQ - R14_FIQ" can be used?
In the FIQ mode, is "R8 - R13" not used?