In AD9361 ip core in which block converts data into Bipolar form.
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Depending on what type of FPGA you are using, the verilog modules implementing the interface can be found at:
hdl/library/axi_ad9361/altera at master · analogdevicesinc/hdl · GitHub
hdl/library/axi_ad9361/xilinx at master · analogdevicesinc/hdl · GitHub
Description of the HDL IP architecture (still under development) can be found at:
Generic AXI ADC IP core [Analog Devices Wiki]
Generic AXI DAC IP core [Analog Devices Wiki]
I moved this question to the Wide Band RF Transceiver community. Someone here should be able to assist you.
HDL design is available in below link.
Moving to FPGA subspace for comments.
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