Dear Forum Members,
i am trying to make an audio DAC with the now obsolete AD1865. I know newer ones exist, but i like to experiment. I need a circuit that converts the signal from I2S to the required format, but i am having problems understanding the documentation. The DAC is 18 bits compatible, but i would like it to be compatible with 16 and 24 bits. The documentation clearly states that the last 18 bits that were clocked in to the DAC will be sent to the outputs when the latch pin is high. However, if i have 16 bits coming from an I2S bus, the last 2 bits will not be filled, before setting the latch pin. My question is: does the input serial register delete it's contents after enabling the latch pin, or will the remaining 2 bits filled with the next 16 bit data's first two bits? Also, if i input 24 bits into it, will the last 6 bits truncated and ignored? And how about the clock requirements? 13.5MHz is the minimum but how much is the maximum?