The Datasheet for the AD9850 says in the opening paragraph that :
"The AD9850’s circuit architecture allows the generation of output frequencies of up to one-half the reference clock frequency (or 62.5 MHz)"
Later it refines that to:
"To apply the AD9850 as a clock generator, limit the selected output frequency to <33% of reference clock frequency, and thereby avoid generating aliased signals that fall within, or close to, the output band of interest".
We would need a 62.5 MHz top end frequency to use as an internal clock - if we do that :
a) how badly affected would the generated clock be ?
b) any recomendations to work around this - are there best practice for filtering etc that you could recommend ?
Alternative is that we always use a lower clock frequency and use an FPGA PLL to scale it 2x.
Many thanks !