Dear Forum.

The Datasheet for the AD9850 says in the opening paragraph that :

"The AD9850’s circuit architecture allows the generation of output frequencies of up to one-half the reference clock frequency (or 62.5 MHz)"

Later it refines that to:

"To apply the AD9850 as a clock generator, limit the selected output frequency to <33% of reference clock frequency, and thereby avoid generating aliased signals that fall within, or close to, the output band of interest".

We would need a 62.5 MHz top end frequency to use as an internal clock - if we do that :

a) how badly affected would the generated clock be ?

b) any recomendations to work around this - are there best practice for filtering etc that you could recommend ?

Alternative is that we always use a lower clock frequency and use an FPGA PLL to scale it 2x.

Many thanks !

boris.

If your end requirement is the generation of a 62.5MHz signal, then the AD9850 is not the best choice. Because the AD9850 is a device that relies on digital sampling techniques (true for all of ADxxxx series of DDSs), it has the usual Nyquist constraints. Namely, it cannot produce fundamental frequencies beyond 1/2 of the sampling frequency. In the case of the AD9850, the maximum sampling frequency (Fs) is 125MHz with a corresponding Nyquist limit of 62.5MHz (hence, the "one-half the reference clock" statement).

Because of the sampled nature of the device, the output signal constitutes a "sampled" sine wave. Hence, the need for an external reconstruction filter at the output. The reconstruction filter limits the output frequency to some value below Fs/2 in order to filter out unwanted spurious components leaving a relatively pure sine wave. Unfortunately, it is not possible to design a filter with a "brick wall" cutoff, so you are forced to choose a cutoff frequency below Fs/2. A reasonable cutoff frequency is ~Fs/3 (hence, the "<33%" statement).

Your suggestion of generating an output signal below 62.5MHz and multiplying it with a PLL will work. However, you must take into consideration how the PLL will deal with the spurious output of the DDS. In my opinion, you are better off choosing a DDS with a higher sampling rate and generate the desired 62.5MHz directly with the DDS.

The AD9851 might be a suitable candidate. The AD9851 samples at up to 180MHz, which would work nicely. With Fs=180MHz the desired output frequency (62.5MHz) is ~35% of the sample rate, making it possible to design a suitable reconstruction filter. The filter design should start to roll off at ~70MHz and reach the desired level of attenuation (typically below -60dBc) at 90MHz.