I am making a new design the JESD204B Clock Generator AD9528 recently, but i met a problem with the PLL, both of the PLL1 and PLL2 of AD9528 can not be lock after configuration。
The loopfilter of PLL1 is design with ADI Clock simulate tool ADIsimCLK like below：
The register value is generated with the AD9528 Evaluation Software and the division factor is like below:
Of course I have already tried many other configuration values about the PLL1 loopfilter,the PLL2 loopfilter and the PDF frequency,but none of them worked.
The VCXO‘s part number in our design is VTEUPLLANF-125.000000,the attachment is the datasheet of the VCXO and one of the configuration files generated by ADIsimCLK and AD9528 Evaluation Software, I wish that you may offer some helpful advise for me, thank you！