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FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz

Question asked by cerasic on Jan 2, 2018
Latest reply on Jan 9, 2018 by cerasic

Hello friends,

happy new year to all of you, I hope this year goes all well and happy for you and your family.

I come to my question, as I mentionned on old posts, I 'm working on FMCDAQ2 and xilinx carrier KC705, I'm using the version 2017_R1 hdl and No-OS, When I use DDS mode, it works fine, I have used the mode ADC 300Mhz DAC 600Mhz (included in the RX path) because my Design works only up to 300Mhz  (I connect the DAC to ADC inputs externally with SMA cable), until here every thing works fine. I want now to improve the spectrum and change  to the configuration ADC1000Mhz DAC1000Mhz,  and want to decimate the ADC output by 4 to get 250Mhz data.

My first trial was to use 1 sample of 64 bits rx bus (which carries 4 samples), but data is not filtered, the spectrum is clean, The option is to use the ADC Decimation filter of AD9680, so I set the AD9680 in decimation mode

with these register values:

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Register 0x200 = 0x22 (two DDCs; I only selected)      Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x49 (real mixer; 6 dB gain)
Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B; DDC 1 Q input = ADC Channel B)
FTW and POW Register 0x314, Register 0x315, Register 0x320, Register 0x321 = 00
FTW and POW Register 0x334, Register 0x335, Register 0x340, Register 0x341 = 00

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BUT IN THESE CASE I GET THE MESSAGE JESD20B_LOCK_STATUS   PLL not LOCKED

I thing I have to adapt the JESD204B parameters to the ADC Decimation.

IS it possible to use these case with AD JESD204B IP ? IF yes how can I adapt the parameters to cope with this frequency, and also  is my ADC decimation setting absolutely correct ?

 

Thanks very much for help and support,

               Kind regards

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